diff options
| author | Markos Chandras <markos.chandras@imgtec.com> | 2016-02-03 03:15:22 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 14:01:48 +0200 |
| commit | 04d83f948510f17f8f2ab320b2386f4b5fbd0bd4 (patch) | |
| tree | e6314877cefa4d165ff645397c12fc17bbd23b22 /arch/mips/kernel/pm-cps.c | |
| parent | f270d881fa552c9c21c37417af2bf95da9a74347 (diff) | |
MIPS: traps: Make sure secondary cores have a sane ebase register
We shouldn't trust that the secondary cores will have a sane ebase register
(either from the bootloader or during the hardware design phase) so use the
ebase address as calculated by the boot CPU.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Petri Gynther <pgynther@google.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12328/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/pm-cps.c')
0 files changed, 0 insertions, 0 deletions