diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2023-02-21 13:16:57 +0000 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-03-14 17:06:16 +0100 |
| commit | 162e134aedcacc9ab9d5648349ceb5409f9ec880 (patch) | |
| tree | 8a5accfa6b37215a60edca63e98fc45f0c449c00 /arch/mips/loongson64 | |
| parent | 227003cb5325298a26276f49bebbfaf39d903be4 (diff) | |
MIPS: Loongson64: Remove CPU_HAS_WB
Q: Do we have really have write buffer
A: Yes, on newer Loongson processors there is a "store fill buffer"
that will collect *cached* writes, on all Loongson processors
AXI crossbar will buffer all writes.
Q: Then why do we want to remove CPU_HAS_WB?
A: Because CPU_HAS_WB introduces wbflush, which intends to flush
all write reuqests to mmio device. We won't be affected by store
fill buffer because it won't buffer uncached writes. And a regular
memory barrier is sufficient to flush crossbar write buffer.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/loongson64')
| -rw-r--r-- | arch/mips/loongson64/setup.c | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/mips/loongson64/setup.c b/arch/mips/loongson64/setup.c index 3cd11c2b308b..257038e18779 100644 --- a/arch/mips/loongson64/setup.c +++ b/arch/mips/loongson64/setup.c @@ -6,7 +6,6 @@ #include <linux/export.h> #include <linux/init.h> -#include <asm/wbflush.h> #include <asm/bootinfo.h> #include <linux/libfdt.h> #include <linux/of_fdt.h> @@ -17,20 +16,6 @@ void *loongson_fdt_blob; -static void wbflush_loongson(void) -{ - asm(".set\tpush\n\t" - ".set\tnoreorder\n\t" - ".set mips3\n\t" - "sync\n\t" - "nop\n\t" - ".set\tpop\n\t" - ".set mips0\n\t"); -} - -void (*__wbflush)(void) = wbflush_loongson; -EXPORT_SYMBOL(__wbflush); - void __init plat_mem_setup(void) { if (loongson_fdt_blob) |