Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:
 "The most notable new addition inside this pull request is the support
  for MIPS's latest and greatest core called "inter/proAptiv".  The
  patch series describes this core as follows.

    "The interAptiv is a power-efficient multi-core microprocessor
     for use in system-on-chip (SoC) applications. The interAptiv combines
     a multi-threading pipeline with a coherence manager to deliver improved
     computational throughput and power efficiency. The interAptiv can
     contain one to four MIPS32R3 interAptiv cores, system level
     coherence manager with L2 cache, optional coherent I/O port,
     and optional floating point unit."

  The platform specific patches touch all 3 Broadcom families.  It adds
  support for the new Broadcom/Netlogix XLP9xx Soc, building a common
  BCM63XX SMP kernel for all BCM63XX SoCs regardless of core type/count
  and full gpio button/led descriptions for BCM47xx.

  The rest of the series are cleanups and bug fixes that are MIPS
  generic and consist largely of changes that Imgtec/MIPS had published
  in their linux-mti-3.10.git stable tree.  Random other cleanups and
  patches preparing code to be merged in 3.15"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (139 commits)
  mips: select ARCH_MIGHT_HAVE_PC_SERIO
  mips: delete non-required instances of include <linux/init.h>
  MIPS: KVM: remove shadow_tlb code
  MIPS: KVM: use common EHINV aware UNIQUE_ENTRYHI
  mips/ide: flush dcache also if icache does not snoop dcache
  MIPS: BCM47XX: fix position of cpu_wait disabling
  MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
  MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>
  MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>
  MIPS: ZBOOT: gather string functions into string.c
  arch/mips/pci: don't check resource with devm_ioremap_resource
  arch/mips/lantiq/xway: don't check resource with devm_ioremap_resource
  bcma: gpio: don't cast u32 to unsigned long
  ssb: gpio: add own IRQ domain
  MIPS: BCM47XX: fix sparse warnings in board.c
  MIPS: BCM47XX: add board detection for Linksys WRT54GS V1
  MIPS: BCM47XX: fix detection for some boards
  MIPS: BCM47XX: Enable buttons support on SSB
  MIPS: BCM47XX: Convert WNDR4500 to new syntax
  MIPS: BCM47XX: Use "timer" trigger for status LEDs
  ...

1 files changed, 36 insertions, 6 deletions

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index efe008846ed0..506925b2c3f3 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -417,14 +417,20 @@ static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
 			case mm_mtc1_op:
 			case mm_cfc1_op:
 			case mm_ctc1_op:
+			case mm_mfhc1_op:
+			case mm_mthc1_op:
 				if (insn.mm_fp1_format.op == mm_mfc1_op)
 					op = mfc_op;
 				else if (insn.mm_fp1_format.op == mm_mtc1_op)
 					op = mtc_op;
 				else if (insn.mm_fp1_format.op == mm_cfc1_op)
 					op = cfc_op;
-				else
+				else if (insn.mm_fp1_format.op == mm_ctc1_op)
 					op = ctc_op;
+				else if (insn.mm_fp1_format.op == mm_mfhc1_op)
+					op = mfhc_op;
+				else
+					op = mthc_op;
 				mips32_insn.fp1_format.opcode = cop1_op;
 				mips32_insn.fp1_format.op = op;
 				mips32_insn.fp1_format.rt =
@@ -853,20 +859,20 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
  * In the Linux kernel, we support selection of FPR format on the
  * basis of the Status.FR bit.	If an FPU is not present, the FR bit
  * is hardwired to zero, which would imply a 32-bit FPU even for
- * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
+ * 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
  * FPU emu is slow and bulky and optimizing this function offers fairly
  * sizeable benefits so we try to be clever and make this function return
  * a constant whenever possible, that is on 64-bit kernels without O32
- * compatibility enabled and on 32-bit kernels.
+ * compatibility enabled and on 32-bit without 64-bit FPU support.
  */
 static inline int cop1_64bit(struct pt_regs *xcp)
 {
 #if defined(CONFIG_64BIT) && !defined(CONFIG_MIPS32_O32)
 	return 1;
-#elif defined(CONFIG_64BIT) && defined(CONFIG_MIPS32_O32)
-	return !test_thread_flag(TIF_32BIT_REGS);
-#else
+#elif defined(CONFIG_32BIT) && !defined(CONFIG_MIPS_O32_FP64_SUPPORT)
 	return 0;
+#else
+	return !test_thread_flag(TIF_32BIT_FPREGS);
 #endif
 }
 
@@ -878,6 +884,10 @@ static inline int cop1_64bit(struct pt_regs *xcp)
 			ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
 			ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
 
+#define SIFROMHREG(si, x)	((si) = (int)(ctx->fpr[x] >> 32))
+#define SITOHREG(si, x)		(ctx->fpr[x] = \
+				ctx->fpr[x] << 32 >> 32 | (u64)(si) << 32)
+
 #define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)])
 #define DITOREG(di, x)	(ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di))
 
@@ -1055,6 +1065,25 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 			break;
 #endif
 
+		case mfhc_op:
+			if (!cpu_has_mips_r2)
+				goto sigill;
+
+			/* copregister rd -> gpr[rt] */
+			if (MIPSInst_RT(ir) != 0) {
+				SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
+					MIPSInst_RD(ir));
+			}
+			break;
+
+		case mthc_op:
+			if (!cpu_has_mips_r2)
+				goto sigill;
+
+			/* copregister rd <- gpr[rt] */
+			SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
+			break;
+
 		case mfc_op:
 			/* copregister rd -> gpr[rt] */
 			if (MIPSInst_RT(ir) != 0) {
@@ -1263,6 +1292,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
 #endif
 
 	default:
+sigill:
 		return SIGILL;
 	}