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authorAleksandar Markovic <aleksandar.markovic@imgtec.com>2017-08-21 14:24:49 +0200
committerRalf Baechle <ralf@linux-mips.org>2017-08-29 15:21:56 +0200
commite1231dd6b1cfbed9dfda5de488ce23c2414e1f04 (patch)
treeaa09df505ad525f042e9fabd4e698afb8163b73d /arch/mips/math-emu/cp1emu.c
parent3ec404d88cefbe42d96a46f20f554f8366d64c33 (diff)
MIPS: math-emu: CLASS.D: Zero bits 32-63 of the result
Fix content of CLASS.D output bits 32-63 to match hardware behavior. Prior to this patch, bits 32-63 of CLASS.D output were not initialized, causing different 32-63 bits content of CLASS.D, based on circumstances. However, the hardware consistently returns all these bits zeroed. The documentation is not clear whether these bits should be zero or unpredictable. Since technically "all zero" case still can be viewed as belonging to "unpredictable" class of results, it is better to zero bits 32-63. Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com> Cc: Douglas Leung <douglas.leung@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Maciej W. Rozycki <macro@imgtec.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Cc: Raghu Gandham <raghu.gandham@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17142/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu/cp1emu.c')
-rw-r--r--arch/mips/math-emu/cp1emu.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 58396cb2057a..a4df2200c725 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -2144,8 +2144,8 @@ copcsr:
return SIGILL;
DPFROMREG(fs, MIPSInst_FS(ir));
- rv.w = ieee754dp_2008class(fs);
- rfmt = w_fmt;
+ rv.l = ieee754dp_2008class(fs);
+ rfmt = l_fmt;
break;
}