diff options
| author | Ingo Molnar <mingo@elte.hu> | 2010-03-09 17:11:53 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-03-09 17:11:53 +0100 |
| commit | 548b84166917d6f5e2296123b85ad24aecd3801d (patch) | |
| tree | 0ab0300e23a02df0fe3c0579627e4998bb122c00 /arch/mips/mm/c-octeon.c | |
| parent | cfb581bcd4f8c158c6f2b48bf5e232bb9e6855c0 (diff) | |
| parent | 57d54889cd00db2752994b389ba714138652e60c (diff) | |
Merge commit 'v2.6.34-rc1' into perf/urgent
Conflicts:
tools/perf/util/probe-event.c
Merge reason: Pick up -rc1 and resolve the conflict as well.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/mips/mm/c-octeon.c')
| -rw-r--r-- | arch/mips/mm/c-octeon.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index e06f1af760a7..0f9c488044d1 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void) switch (c->cputype) { case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: config1 = read_c0_config1(); c->icache.linesz = 2 << ((config1 >> 19) & 7); c->icache.sets = 64 << ((config1 >> 22) & 7); @@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void) c->icache.sets * c->icache.ways * c->icache.linesz; c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; c->dcache.linesz = 128; - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) - c->dcache.sets = 1; /* CN3XXX has one Dcache set */ - else + if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ + else + c->dcache.sets = 1; /* CN3XXX has one Dcache set */ c->dcache.ways = 64; dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; @@ -305,4 +306,3 @@ asmlinkage void cache_parity_error_octeon_non_recoverable(void) { cache_parity_error_octeon(1); } - |