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authorIngo Molnar <mingo@kernel.org>2017-08-31 14:20:06 +0200
committerIngo Molnar <mingo@kernel.org>2017-08-31 14:20:06 +0200
commit3e83dfd5d8e374328078f527f1f7d189824896ab (patch)
tree2f82b2e82f7a4b5c513fed42d4228a8bce938180 /arch/mips/pci/pci.c
parent3308376a914b9c3f57a12072c063814403d983a8 (diff)
parent9e52fc2b50de3a1c08b44f94c610fbe998c0031a (diff)
Merge branch 'x86/mm' into x86/platform, to pick up TLB flush dependency
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/mips/pci/pci.c')
-rw-r--r--arch/mips/pci/pci.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index bd67ac74fe2d..9632436d74d7 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -28,16 +28,15 @@ EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
static int __init pcibios_set_cache_line_size(void)
{
- struct cpuinfo_mips *c = &current_cpu_data;
unsigned int lsize;
/*
* Set PCI cacheline size to that of the highest level in the
* cache hierarchy.
*/
- lsize = c->dcache.linesz;
- lsize = c->scache.linesz ? : lsize;
- lsize = c->tcache.linesz ? : lsize;
+ lsize = cpu_dcache_line_size();
+ lsize = cpu_scache_line_size() ? : lsize;
+ lsize = cpu_tcache_line_size() ? : lsize;
BUG_ON(!lsize);