diff options
| author | Tejun Heo <tj@kernel.org> | 2009-08-14 14:41:02 +0900 |
|---|---|---|
| committer | Tejun Heo <tj@kernel.org> | 2009-08-14 14:45:31 +0900 |
| commit | 384be2b18a5f9475eab9ca2bdfa95cc1a04ef59c (patch) | |
| tree | 04c93f391a1b65c8bf8d7ba8643c07d26c26590a /arch/mips/pmc-sierra | |
| parent | a76761b621bcd8336065c4fe3a74f046858bc34c (diff) | |
| parent | 142d44b0dd6741a64a7bdbe029110e7c1dcf1d23 (diff) | |
Merge branch 'percpu-for-linus' into percpu-for-next
Conflicts:
arch/sparc/kernel/smp_64.c
arch/x86/kernel/cpu/perf_counter.c
arch/x86/kernel/setup_percpu.c
drivers/cpufreq/cpufreq_ondemand.c
mm/percpu.c
Conflicts in core and arch percpu codes are mostly from commit
ed78e1e078dd44249f88b1dd8c76dafb39567161 which substituted many
num_possible_cpus() with nr_cpu_ids. As for-next branch has moved all
the first chunk allocators into mm/percpu.c, the changes are moved
from arch code to mm/percpu.c.
Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'arch/mips/pmc-sierra')
| -rw-r--r-- | arch/mips/pmc-sierra/msp71xx/gpio.c | 2 | ||||
| -rw-r--r-- | arch/mips/pmc-sierra/msp71xx/gpio_extended.c | 2 | ||||
| -rw-r--r-- | arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c | 12 | ||||
| -rw-r--r-- | arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c | 2 |
4 files changed, 2 insertions, 16 deletions
diff --git a/arch/mips/pmc-sierra/msp71xx/gpio.c b/arch/mips/pmc-sierra/msp71xx/gpio.c index 69848c5813e2..aaccbe524386 100644 --- a/arch/mips/pmc-sierra/msp71xx/gpio.c +++ b/arch/mips/pmc-sierra/msp71xx/gpio.c @@ -1,6 +1,4 @@ /* - * @file /arch/mips/pmc-sierra/msp71xx/gpio.c - * * Generic PMC MSP71xx GPIO handling. These base gpio are controlled by two * types of registers. The data register sets the output level when in output * mode and when in input mode will contain the value at the input. The config diff --git a/arch/mips/pmc-sierra/msp71xx/gpio_extended.c b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c index fc6dbc6cf1c0..2a99f360fae4 100644 --- a/arch/mips/pmc-sierra/msp71xx/gpio_extended.c +++ b/arch/mips/pmc-sierra/msp71xx/gpio_extended.c @@ -1,6 +1,4 @@ /* - * @file /arch/mips/pmc-sierra/msp71xx/gpio_extended.c - * * Generic PMC MSP71xx EXTENDED (EXD) GPIO handling. The extended gpio is * a set of hardware registers that have no need for explicit locking as * it is handled by unique method of writing individual set/clr bits. diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c index f5f1b8d2bb9a..61f390232346 100644 --- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c +++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c @@ -45,13 +45,6 @@ static inline void mask_msp_slp_irq(unsigned int irq) */ static inline void ack_msp_slp_irq(unsigned int irq) { - mask_slp_irq(irq); - - /* - * only really necessary for 18, 16-14 and sometimes 3:0 (since - * these can be edge sensitive) but it doesn't hurt for the others. - */ - /* check for PER interrupt range */ if (irq < MSP_PER_INTBASE) *SLP_INT_STS_REG = (1 << (irq - MSP_SLP_INTBASE)); @@ -62,8 +55,7 @@ static inline void ack_msp_slp_irq(unsigned int irq) static struct irq_chip msp_slp_irq_controller = { .name = "MSP_SLP", .ack = ack_msp_slp_irq, - .mask = ack_msp_slp_irq, - .mask_ack = ack_msp_slp_irq, + .mask = mask_msp_slp_irq, .unmask = unmask_msp_slp_irq, }; @@ -79,7 +71,7 @@ void __init msp_slp_irq_init(void) /* initialize all the IRQ descriptors */ for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++) - set_irq_chip_and_handler(i, &msp_slp_irq_controller + set_irq_chip_and_handler(i, &msp_slp_irq_controller, handle_level_irq); } diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c index caf5e9a0acc7..fc990cb31941 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c @@ -1,6 +1,4 @@ /* - * arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c - * * Copyright (C) 2003 PMC-Sierra Inc. * Author: Manish Lachwani (lachwani@pmc-sierra.com) * |