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authorJohn Crispin <blogic@openwrt.org>2013-08-23 08:31:32 +0200
committerRalf Baechle <ralf@linux-mips.org>2013-09-04 16:58:06 +0200
commit0d4649684ca6cbc536fcc509e7aac0b34bb4146a (patch)
treed1efbf82bb324384eff026d0314ca1ac755c02a3 /arch/mips/ralink/mt7620.c
parent68c9b7ed9ead9c5b38c2efa690b6bdae00a09d8c (diff)
MIPS: ralink: mt7620: Add spi clock definition
Register a clock device for the SPI block of the MT7620 SoC. The clock device will be used by the SPI host controller driver to determine the base clock of the controller. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5754/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/ralink/mt7620.c')
-rw-r--r--arch/mips/ralink/mt7620.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index 7759c5a59a5d..d217509e5300 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -318,6 +318,7 @@ void __init ralink_clk_init(void)
ralink_clk_add("10000100.timer", periph_rate);
ralink_clk_add("10000120.watchdog", periph_rate);
ralink_clk_add("10000500.uart", periph_rate);
+ ralink_clk_add("10000b00.spi", sys_rate);
ralink_clk_add("10000c00.uartlite", periph_rate);
}