diff options
| author | Sergio Paracuellos <sergio.paracuellos@gmail.com> | 2023-06-19 06:09:39 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-06-21 14:50:23 +0200 |
| commit | 201ddc05777cd8e084b508bcdda22214bfe2895e (patch) | |
| tree | 4a0799b994e622902699b0f5a05e530cbe66861b /arch/mips/ralink/of.c | |
| parent | 04b153abdfcbaba70ceef5a846067d4447fd0078 (diff) | |
mips: ralink: remove reset related code
A proper clock driver for ralink SoCs has been added. This driver is also
a reset provider for the SoC. Hence there is no need to have reset related
code in 'arch/mips/ralink' folder anymore. The only code that remains is
the one related with mips_reboot_setup where a PCI reset is performed.
We maintain this because I cannot test old ralink board with PCI to be
sure all works if we remove also this code.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/ralink/of.c')
| -rw-r--r-- | arch/mips/ralink/of.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c index 4d06de77d92a..df29e6c896aa 100644 --- a/arch/mips/ralink/of.c +++ b/arch/mips/ralink/of.c @@ -81,10 +81,6 @@ static int __init plat_of_setup(void) { __dt_register_buses(soc_info.compatible, "palmbus"); - /* make sure that the reset controller is setup early */ - if (ralink_soc != MT762X_SOC_MT7621AT) - ralink_rst_init(); - return 0; } |