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authorSergio Paracuellos <sergio.paracuellos@gmail.com>2023-02-27 11:58:02 +0100
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2023-03-14 17:13:50 +0100
commit5a5aa151bdccea934d4a84086661538b60a09a42 (patch)
tree5df02e65ad33dffb7958fa7b5088879645bd0566 /arch/mips/ralink
parent1e688601d18d3d872ffaad70c599e8c1a1d788a0 (diff)
mips: ralink: rt288x: soc queries and tests as functions
Move the SoC register value queries and tests to specific functions, to remove repetition of logic. No functional changes intended Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/ralink')
-rw-r--r--arch/mips/ralink/rt288x.c63
1 files changed, 47 insertions, 16 deletions
diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
index 12f339138c4c..a417b8b89b94 100644
--- a/arch/mips/ralink/rt288x.c
+++ b/arch/mips/ralink/rt288x.c
@@ -57,29 +57,60 @@ void __init ralink_of_remap(void)
panic("Failed to remap core resources");
}
-void __init prom_soc_init(struct ralink_soc_info *soc_info)
+static unsigned int __init rt2880_get_soc_name0(void)
{
- const char *name;
- u32 n0;
- u32 n1;
- u32 id;
+ return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0);
+}
- n0 = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME0);
- n1 = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1);
- id = __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID);
+static unsigned int __init rt2880_get_soc_name1(void)
+{
+ return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_NAME1);
+}
- if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
+static bool __init rt2880_soc_valid(void)
+{
+ if (rt2880_get_soc_name0() == RT2880_CHIP_NAME0 &&
+ rt2880_get_soc_name1() == RT2880_CHIP_NAME1)
+ return true;
+ else
+ return false;
+}
+
+static const char __init *rt2880_get_soc_name(void)
+{
+ if (rt2880_soc_valid())
+ return "RT2880";
+ else
+ return "invalid";
+}
+
+static unsigned int __init rt2880_get_soc_id(void)
+{
+ return __raw_readl(RT2880_SYSC_BASE + SYSC_REG_CHIP_ID);
+}
+
+static unsigned int __init rt2880_get_soc_ver(void)
+{
+ return (rt2880_get_soc_id() >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK;
+}
+
+static unsigned int __init rt2880_get_soc_rev(void)
+{
+ return (rt2880_get_soc_id() & CHIP_ID_REV_MASK);
+}
+void __init prom_soc_init(struct ralink_soc_info *soc_info)
+{
+ if (rt2880_soc_valid())
soc_info->compatible = "ralink,r2880-soc";
- name = "RT2880";
- } else {
- panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
- }
+ else
+ panic("rt288x: unknown SoC, n0:%08x n1:%08x",
+ rt2880_get_soc_name0(), rt2880_get_soc_name1());
snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
"Ralink %s id:%u rev:%u",
- name,
- (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
- (id & CHIP_ID_REV_MASK));
+ rt2880_get_soc_name(),
+ rt2880_get_soc_ver(),
+ rt2880_get_soc_rev());
soc_info->mem_base = RT2880_SDRAM_BASE;
soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;