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authorMaciej W. Rozycki <macro@linux-mips.org>2013-09-17 16:58:10 +0100
committerRalf Baechle <ralf@linux-mips.org>2013-09-18 20:25:19 +0200
commit8ff374b9c296b96484d5e63b45b22d0862ffee8f (patch)
tree0a40c8b881b985854a58793b14ca7b4de9c6f123 /arch/mips/sibyte/sb1250/setup.c
parentb42b4f3af8b1ac2f7b09781d523bf918f366d8d6 (diff)
MIPS: Cleanup CP0 PRId and CP1 FPIR register access masks
Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout. The change does not touch places that use shifted or partial masks. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5838/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte/sb1250/setup.c')
-rw-r--r--arch/mips/sibyte/sb1250/setup.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index a14bd4cb0bc0..3c02b2a77ae9 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -22,6 +22,7 @@
#include <linux/string.h>
#include <asm/bootinfo.h>
+#include <asm/cpu.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <asm/sibyte/sb1250.h>
@@ -182,7 +183,7 @@ void __init sb1250_setup(void)
int plldiv;
int bad_config = 0;
- sb1_pass = read_c0_prid() & 0xff;
+ sb1_pass = read_c0_prid() & PRID_REV_MASK;
sys_rev = __raw_readq(IOADDR(A_SCD_SYSTEM_REVISION));
soc_type = SYS_SOC_TYPE(sys_rev);
soc_pass = G_SYS_REVISION(sys_rev);