summaryrefslogtreecommitdiff
path: root/arch/mips
diff options
context:
space:
mode:
authorVladimir Oltean <vladimir.oltean@nxp.com>2021-08-19 20:04:16 +0300
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2021-08-21 10:38:48 +0200
commiteba54cbb92d28b4f6dc1ed5f73f5187b09d82c08 (patch)
treee9736a4be9c888c90ac6f2c9720d4093dcb79849 /arch/mips
parent0181f6f19c6c35b24f1516d8db22f3bbce762633 (diff)
MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports
The ocelot driver was converted to phylink, and that expects a valid phy_interface_t. Without a phy-mode, of_get_phy_mode returns PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that. The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we should fix the device trees and specify the phy-mode too. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/boot/dts/mscc/ocelot_pcb120.dts4
-rw-r--r--arch/mips/boot/dts/mscc/ocelot_pcb123.dts4
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index d2dc6b3d923c..bd240690cb37 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -71,21 +71,25 @@
&port0 {
status = "okay";
phy-handle = <&phy0>;
+ phy-mode = "internal";
};
&port1 {
status = "okay";
phy-handle = <&phy1>;
+ phy-mode = "internal";
};
&port2 {
status = "okay";
phy-handle = <&phy2>;
+ phy-mode = "internal";
};
&port3 {
status = "okay";
phy-handle = <&phy3>;
+ phy-mode = "internal";
};
&port4 {
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
index 7d7e638791dd..0185045c7630 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -49,19 +49,23 @@
&port0 {
status = "okay";
phy-handle = <&phy0>;
+ phy-mode = "internal";
};
&port1 {
status = "okay";
phy-handle = <&phy1>;
+ phy-mode = "internal";
};
&port2 {
status = "okay";
phy-handle = <&phy2>;
+ phy-mode = "internal";
};
&port3 {
status = "okay";
phy-handle = <&phy3>;
+ phy-mode = "internal";
};