diff options
| author | David Howells <dhowells@redhat.com> | 2018-03-08 09:48:46 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2018-03-09 23:19:56 +0100 |
| commit | 739d875dd6982618020d30f58f8acf10f6076e6d (patch) | |
| tree | 13deb11d5b2078e49d4e5b6175e5846a22a04b95 /arch/mn10300/mm/cache-dbg-inv-by-reg.S | |
| parent | b67aea2bbab780e412b8af3386cc9f78f61a4cac (diff) | |
mn10300: Remove the architecture
Remove the MN10300 arch as the hardware is defunct.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: David Howells <dhowells@redhat.com>
cc: Masahiro Yamada <yamada.masahiro@socionext.com>
cc: linux-am33-list@redhat.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/mn10300/mm/cache-dbg-inv-by-reg.S')
| -rw-r--r-- | arch/mn10300/mm/cache-dbg-inv-by-reg.S | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/arch/mn10300/mm/cache-dbg-inv-by-reg.S b/arch/mn10300/mm/cache-dbg-inv-by-reg.S deleted file mode 100644 index c4e6252941b1..000000000000 --- a/arch/mn10300/mm/cache-dbg-inv-by-reg.S +++ /dev/null @@ -1,69 +0,0 @@ -/* MN10300 CPU cache invalidation routines, using automatic purge registers - * - * Copyright (C) 2011 Red Hat, Inc. All Rights Reserved. - * Written by David Howells (dhowells@redhat.com) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public Licence - * as published by the Free Software Foundation; either version - * 2 of the Licence, or (at your option) any later version. - */ -#include <linux/sys.h> -#include <linux/linkage.h> -#include <asm/cache.h> -#include <asm/irqflags.h> -#include <asm/cacheflush.h> -#include "cache.inc" - - .am33_2 - - .globl debugger_local_cache_flushinv_one - -############################################################################### -# -# void debugger_local_cache_flushinv_one(u8 *addr) -# -# Invalidate one particular cacheline if it's in the icache -# -############################################################################### - ALIGN - .globl debugger_local_cache_flushinv_one - .type debugger_local_cache_flushinv_one,@function -debugger_local_cache_flushinv_one: - mov d0,a1 - - mov CHCTR,a0 - movhu (a0),d0 - btst CHCTR_ICEN,d0 - beq mn10300_local_icache_inv_range_reg_end - - LOCAL_CLI_SAVE(d1) - - mov ICIVCR,a0 - - # wait for the invalidator to quiesce - setlb - mov (a0),d0 - btst ICIVCR_ICIVBSY,d0 - lne - - # set the mask - mov ~L1_CACHE_TAG_MASK,d0 - mov d0,(ICIVMR) - - # invalidate the cache line at the given address - and ~L1_CACHE_TAG_MASK,a1 - or ICIVCR_ICI,a1 - mov a1,(a0) - - # wait for the invalidator to quiesce again - setlb - mov (a0),d0 - btst ICIVCR_ICIVBSY,d0 - lne - - LOCAL_IRQ_RESTORE(d1) - -mn10300_local_icache_inv_range_reg_end: - ret [],0 - .size debugger_local_cache_flushinv_one,.-debugger_local_cache_flushinv_one |