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authorPeter Zijlstra <peterz@infradead.org>2021-04-14 14:45:43 +0200
committerStafford Horne <shorne@gmail.com>2021-05-15 16:00:10 +0900
commit8b549c18ae81dbc36fb11e4aa08b8378c599ca95 (patch)
treea639f8a9307a3649e56b39bd0f3adc6ec4d055c1 /arch/openrisc
parent371dcaee1ade4b1eefd541ae6ee048b5ce15b37c (diff)
openrisc: Define memory barrier mb
This came up in the discussion of the requirements of qspinlock on an architecture. OpenRISC uses qspinlock, but it was noticed that the memmory barrier was not defined. Peter defined it in the mail thread writing: As near as I can tell this should do. The arch spec only lists this one instruction and the text makes it sound like a completion barrier. This is correct so applying this patch. Signed-off-by: Peter Zijlstra <peterz@infradead.org> [shorne@gmail.com:Turned the mail into a patch] Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc')
-rw-r--r--arch/openrisc/include/asm/barrier.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/openrisc/include/asm/barrier.h b/arch/openrisc/include/asm/barrier.h
new file mode 100644
index 000000000000..7538294721be
--- /dev/null
+++ b/arch/openrisc/include/asm/barrier.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_BARRIER_H
+#define __ASM_BARRIER_H
+
+#define mb() asm volatile ("l.msync" ::: "memory")
+
+#include <asm-generic/barrier.h>
+
+#endif /* __ASM_BARRIER_H */