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authorDaniel Vetter <daniel.vetter@ffwll.ch>2019-10-23 12:02:47 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2019-10-23 12:10:05 +0200
commit2e79e22e092acd55da0b2db066e4826d7d152c41 (patch)
treee7ec9782c0b7831c511af711424126a2b9a4eb07 /arch/parisc/include/asm/cache.h
parentf1b4a9217efd61d0b84c6dc404596c8519ff6f59 (diff)
parent7d194c2100ad2a6dded545887d02754948ca5241 (diff)
Merge v5.4-rc4 into drm-next
Thierry needs fd70c7755bf0 ("drm/bridge: tc358767: fix max_tu_symbol value") to be able to merge his dp_link patch series. Some adjacent changes conflicts, plus some clashes in i915 due to cherry-picking and git trying to be helpful and leaving both versions in. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/parisc/include/asm/cache.h')
-rw-r--r--arch/parisc/include/asm/cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 73ca89a47f49..e5de3f897633 100644
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -22,7 +22,7 @@
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
-#define __read_mostly __attribute__((__section__(".data..read_mostly")))
+#define __read_mostly __section(.data..read_mostly)
void parisc_cache_init(void); /* initializes cache-flushing */
void disable_sr_hashing_asm(int); /* low level support for above */