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authorHelge Deller <deller@gmx.de>2017-01-08 11:01:11 +0100
committerHelge Deller <deller@gmx.de>2017-05-10 17:46:14 +0200
commitc8c3735997a3aa184fa81742bb6c4062a26af2f3 (patch)
tree3d6e8864e8935ac167efc3313913444b4eb2e811 /arch/parisc/kernel/time.c
parentc3e5523fcffdc9df8faa7d66f5ad8c1c833e1795 (diff)
parisc: Enhance detection of synchronous cr16 clocksources
The cr16 clocks of the physical PARISC CPUs are usually nonsynchronous. Nevertheless, it seems that each CPU socket (which holds two cores) of PA8800 and PA8900 CPUs (e.g. in a C8000 workstation) is fed by the same clock source, which makes the cr16 clocks of each CPU socket syncronous. Let's try to detect such situations and mark the cr16 clocksource stable on single-socket and single-core machines. Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc/kernel/time.c')
-rw-r--r--arch/parisc/kernel/time.c24
1 files changed, 20 insertions, 4 deletions
diff --git a/arch/parisc/kernel/time.c b/arch/parisc/kernel/time.c
index 89421df70160..2d956aa0a38a 100644
--- a/arch/parisc/kernel/time.c
+++ b/arch/parisc/kernel/time.c
@@ -243,14 +243,30 @@ void __init time_init(void)
static int __init init_cr16_clocksource(void)
{
/*
- * The cr16 interval timers are not syncronized across CPUs, so mark
- * them unstable and lower rating on SMP systems.
+ * The cr16 interval timers are not syncronized across CPUs on
+ * different sockets, so mark them unstable and lower rating on
+ * multi-socket SMP systems.
*/
if (num_online_cpus() > 1) {
- clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
- clocksource_cr16.rating = 0;
+ int cpu;
+ unsigned long cpu0_loc;
+ cpu0_loc = per_cpu(cpu_data, 0).cpu_loc;
+
+ for_each_online_cpu(cpu) {
+ if (cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc)
+ continue;
+
+ clocksource_cr16.name = "cr16_unstable";
+ clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
+ clocksource_cr16.rating = 0;
+ break;
+ }
}
+ /* XXX: We may want to mark sched_clock stable here if cr16 clocks are
+ * in sync:
+ * (clocksource_cr16.flags == CLOCK_SOURCE_IS_CONTINUOUS) */
+
/* register at clocksource framework */
clocksource_register_hz(&clocksource_cr16,
100 * PAGE0->mem_10msec);