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authorHelge Deller <deller@gmx.de>2019-05-07 20:19:05 +0200
committerHelge Deller <deller@gmx.de>2019-05-10 21:00:24 +0200
commite6eb5fe9123f05dcbf339ae5c0b6d32fcc0685d5 (patch)
treeaf8322072981c930ac0ac33e62ee5b6d0732fc95 /arch/parisc
parent62217beb394e654bbd2bb87c533dadd2d8bf62c6 (diff)
parisc: Drop LDCW barrier in CAS code when running UP
When running an SMP kernel on a single-CPU machine, we can speed up the CAS code by replacing the LDCW sync barrier with NOP. Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc')
-rw-r--r--arch/parisc/kernel/syscall.S12
1 files changed, 8 insertions, 4 deletions
diff --git a/arch/parisc/kernel/syscall.S b/arch/parisc/kernel/syscall.S
index e54d5e4d3489..97ac707c6bff 100644
--- a/arch/parisc/kernel/syscall.S
+++ b/arch/parisc/kernel/syscall.S
@@ -641,7 +641,8 @@ cas_action:
2: stw %r24, 0(%r26)
/* Free lock */
#ifdef CONFIG_SMP
- LDCW 0(%sr2,%r20), %r1 /* Barrier */
+98: LDCW 0(%sr2,%r20), %r1 /* Barrier */
+99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif
stw %r20, 0(%sr2,%r20)
#if ENABLE_LWS_DEBUG
@@ -658,7 +659,8 @@ cas_action:
/* Error occurred on load or store */
/* Free lock */
#ifdef CONFIG_SMP
- LDCW 0(%sr2,%r20), %r1 /* Barrier */
+98: LDCW 0(%sr2,%r20), %r1 /* Barrier */
+99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif
stw %r20, 0(%sr2,%r20)
#if ENABLE_LWS_DEBUG
@@ -862,7 +864,8 @@ cas2_action:
cas2_end:
/* Free lock */
#ifdef CONFIG_SMP
- LDCW 0(%sr2,%r20), %r1 /* Barrier */
+98: LDCW 0(%sr2,%r20), %r1 /* Barrier */
+99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif
stw %r20, 0(%sr2,%r20)
/* Enable interrupts */
@@ -875,7 +878,8 @@ cas2_end:
/* Error occurred on load or store */
/* Free lock */
#ifdef CONFIG_SMP
- LDCW 0(%sr2,%r20), %r1 /* Barrier */
+98: LDCW 0(%sr2,%r20), %r1 /* Barrier */
+99: ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
#endif
stw %r20, 0(%sr2,%r20)
ssm PSW_SM_I, %r0