summaryrefslogtreecommitdiff
path: root/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
diff options
context:
space:
mode:
authorpoonam aggrwal <poonam.aggrwal@freescale.com>2015-09-19 23:45:42 +0530
committerScott Wood <scottwood@freescale.com>2015-10-17 00:36:34 -0500
commit52246445516e99a59f531a8c72bee8f715a5fd1f (patch)
treeec61b0fd82b70db590d51825d6dd6beb4c6e3d55 /arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
parentdc37374b9c83382b91f3804845ae593bedc2d13a (diff)
powerpc/b4860: Renamed the L2 caches
To make provision for more than one L2 caches in the system, change the name from L2 to L2_1; same as in T4 platforms. * Also remove the L2 entry from common file "arch/powerpc/boot/dts/fsl/b4si-post.dtsi" Keep them only in separate files for b4860 and b4420. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi')
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 338af7e39dd9..4257a7739dd1 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -65,14 +65,14 @@
device_type = "cpu";
reg = <0 1>;
clocks = <&mux0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
clocks = <&mux0>;
- next-level-cache = <&L2>;
+ next-level-cache = <&L2_1>;
fsl,portid-mapping = <0x80000000>;
};
};