diff options
| author | Scott Wood <scottwood@freescale.com> | 2014-05-05 20:35:10 -0500 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-05-22 18:10:42 -0500 |
| commit | e83eb028bb980cecc85b050aa626df384723aff2 (patch) | |
| tree | 4e58df362d96f4f5e38d1c0b3b5cc064b88b69c5 /arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | |
| parent | 8cb59788b342903f2912ecef0df4aaadd12e5843 (diff) | |
powerpc/fsl: Add fsl,portid-mapping to corenet1-cf chips
Signed-off-by: Scott Wood <scottwood@freescale.com>
Cc: Diana Craciun <diana.craciun@freescale.com>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi')
| -rw-r--r-- | arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi index fe1a2e6613b4..1cc61e126e4c 100644 --- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi +++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi @@ -90,6 +90,7 @@ reg = <0>; clocks = <&mux0>; next-level-cache = <&L2_0>; + fsl,portid-mapping = <0x80000000>; L2_0: l2-cache { next-level-cache = <&cpc>; }; @@ -99,6 +100,7 @@ reg = <1>; clocks = <&mux1>; next-level-cache = <&L2_1>; + fsl,portid-mapping = <0x40000000>; L2_1: l2-cache { next-level-cache = <&cpc>; }; |