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authorIgal Liberman <Igal.Liberman@freescale.com>2015-08-05 06:42:07 +0300
committerScott Wood <scottwood@freescale.com>2015-10-27 18:14:39 -0500
commitda414bb923d95f1f59fbf534a0e2ef9f52ffc667 (patch)
tree853a86bf7d8fbec2a75d704e331ae043b4083679 /arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
parentd55ad2967d891ef9c48adf46c6d915bec81a9375 (diff)
powerpc/mpc85xx: Add FSL QorIQ DPAA FMan support to the SoC device tree(s)
Based on prior work by Andy Fleming <afleming@freescale.com> Signed-off-by: Shruti Kanetkar <Shruti@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi')
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi10
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index 1cc61e126e4c..bfba0b4f1cbb 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -1,7 +1,7 @@
/*
* P5020/P5010 Silicon/SoC Device Tree Source (pre include)
*
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011 - 2015 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -79,6 +79,14 @@
raideng_jr1 = &raideng_jr1;
raideng_jr2 = &raideng_jr2;
raideng_jr3 = &raideng_jr3;
+
+ fman0 = &fman0;
+ ethernet0 = &enet0;
+ ethernet1 = &enet1;
+ ethernet2 = &enet2;
+ ethernet3 = &enet3;
+ ethernet4 = &enet4;
+ ethernet5 = &enet5;
};
cpus {