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authorCamelia Groza <camelia.groza@nxp.com>2018-09-20 14:47:01 +0300
committerScott Wood <oss@buserror.net>2018-10-20 18:23:56 -0500
commit0400d65501930e6e99848572b3818914c3b94256 (patch)
tree90544b9ecadb7956583dda6650d6cf4f486aabee /arch/powerpc/boot
parenta0e102914aa3f619a5bc68a0d33e17d1788cdf4c (diff)
powerpc/dts/fsl: t2080rdb: reorder the Cortina PHY XFI lanes
According to the T2080RDB schematics, for the CS4315 PHY, the XFI 1 lane is connected to SFP 2 and the XFI 2 lane is connected to SFP 1. Change the device tree to reflect the correct PHY order and port association. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/dts/fsl/t2080rdb.dts4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/boot/dts/fsl/t2080rdb.dts b/arch/powerpc/boot/dts/fsl/t2080rdb.dts
index 55c0210a771d..092a400740f8 100644
--- a/arch/powerpc/boot/dts/fsl/t2080rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t2080rdb.dts
@@ -77,12 +77,12 @@
};
ethernet@f0000 {
- phy-handle = <&xg_cs4315_phy1>;
+ phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
- phy-handle = <&xg_cs4315_phy2>;
+ phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};