diff options
| author | Gautham R. Shenoy <ego@linux.vnet.ibm.com> | 2017-01-25 14:06:25 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-01-31 08:32:12 +1100 |
| commit | 823b7bd5156a93872d9561b3f033dfe5cb80204e (patch) | |
| tree | 1ce3ae29c54e70eab6ef786044fd313e4712c636 /arch/powerpc/include/asm/cpuidle.h | |
| parent | 616badd2fb499320d3ac3b54462f55dededd0e0f (diff) | |
powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro
Currently all the low-power idle states are expected to wake up
at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
that puts the CPU to an idle state and never returns.
On ISA v3.0, when the ESL and EC bits in the PSSCR are zero, the CPU
is expected to wake up at the next instruction of the idle
instruction.
This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the
no-return variant and reuses the name IDLE_STATE_ENTER_SEQ
for a variant that allows resuming operation at the instruction next
to the idle-instruction.
Acked-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/cpuidle.h')
| -rw-r--r-- | arch/powerpc/include/asm/cpuidle.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/cpuidle.h b/arch/powerpc/include/asm/cpuidle.h index 3919332965af..0a3255b12587 100644 --- a/arch/powerpc/include/asm/cpuidle.h +++ b/arch/powerpc/include/asm/cpuidle.h @@ -21,7 +21,7 @@ extern u64 pnv_first_deep_stop_state; /* Idle state entry routines */ #ifdef CONFIG_PPC_P7_NAP -#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ +#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \ /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \ std r0,0(r1); \ ptesync; \ @@ -29,6 +29,9 @@ extern u64 pnv_first_deep_stop_state; 1: cmpd cr0,r0,r0; \ bne 1b; \ IDLE_INST; \ + +#define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \ + IDLE_STATE_ENTER_SEQ(IDLE_INST) \ b . #endif /* CONFIG_PPC_P7_NAP */ |