diff options
| author | Cédric Le Goater <clg@kaod.org> | 2021-07-20 15:42:09 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-08-10 23:15:02 +1000 |
| commit | f5af0a978776b710f16dc99a85496b1e760bf9e0 (patch) | |
| tree | f11b8cfb23d59ceec4cc6718721f09d278481237 /arch/powerpc/include/asm/xive.h | |
| parent | b68c6646cce5ee8caefa6333ee743f960222dcea (diff) | |
KVM: PPC: Book3S HV: XIVE: Add support for automatic save-restore
On P10, the feature doing an automatic "save & restore" of a VCPU
interrupt context is set by default in OPAL. When a VP context is
pulled out, the state of the interrupt registers are saved by the XIVE
interrupt controller under the internal NVP structure representing the
VP. This saves a costly store/load in guest entries and exits.
If OPAL advertises the "save & restore" feature in the device tree,
it should also have set the 'H' bit in the CAM line. Check that when
vCPUs are connected to their ICP in KVM before going any further.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20210720134209.256133-3-clg@kaod.org
Diffstat (limited to 'arch/powerpc/include/asm/xive.h')
| -rw-r--r-- | arch/powerpc/include/asm/xive.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h index 20ae50ab083c..92930b0b5d0e 100644 --- a/arch/powerpc/include/asm/xive.h +++ b/arch/powerpc/include/asm/xive.h @@ -126,6 +126,7 @@ int xive_native_enable_vp(u32 vp_id, bool single_escalation); int xive_native_disable_vp(u32 vp_id); int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id); bool xive_native_has_single_escalation(void); +bool xive_native_has_save_restore(void); int xive_native_get_queue_info(u32 vp_id, uint32_t prio, u64 *out_qpage, |