diff options
| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2015-06-05 16:35:19 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2015-06-11 15:16:51 +1000 |
| commit | bbb845c4bac88d8feffa8945dd28b50849984e30 (patch) | |
| tree | ca2cbb8e0df075d41dc7f200d0f7249bd91665e1 /arch/powerpc/include/asm | |
| parent | 43cb60ab7f8c91b9bf5988edc318dee99ec93b9b (diff) | |
powerpc/powernv: Implement multilevel TCE tables
TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
on huge guests (hundreds of GB of RAM) so the kernel might be unable to
allocate contiguous chunk of physical memory to store the TCE table.
To address this, POWER8 CPU (actually, IODA2) supports multi-level
TCE tables, up to 5 levels which splits the table into a tree of
smaller subtables.
This adds multi-level TCE tables support to
pnv_pci_ioda2_table_alloc_pages() and pnv_pci_ioda2_table_free_pages()
helpers.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/iommu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h index 4636734604d7..706cfc0b1190 100644 --- a/arch/powerpc/include/asm/iommu.h +++ b/arch/powerpc/include/asm/iommu.h @@ -96,6 +96,8 @@ struct iommu_pool { struct iommu_table { unsigned long it_busno; /* Bus number this table belongs to */ unsigned long it_size; /* Size of iommu table in entries */ + unsigned long it_indirect_levels; + unsigned long it_level_size; unsigned long it_offset; /* Offset into global table */ unsigned long it_base; /* mapped address of tce table */ unsigned long it_index; /* which iommu table this is */ |