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authorGavin Shan <gwshan@linux.vnet.ibm.com>2014-04-24 18:00:27 +1000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-04-28 17:35:05 +1000
commitb2b5efcf208ddc9444aca77336627428782a39f4 (patch)
tree8a532861c06c0109f373aa69ad3b58fb692433e3 /arch/powerpc/include
parent35845a7826a27eb1c16ee5b0c5a0307159c1d1c4 (diff)
powerpc/powernv: Fundamental reset on PLX ports
The patch intends to support fundamental reset on PLX downstream ports. If the PCI device matches any one of the internal table, which includes PLX vendor ID, bridge device ID, register offset for fundamental reset and bit, fundamental reset will be done accordingly. Otherwise, it will fail back to hot reset. Additional flag (EEH_DEV_FRESET) is introduced to record the last reset type on the PCI bridge. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/eeh.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index b76f58c124ca..d12529f34524 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -109,6 +109,7 @@ struct eeh_pe {
#define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
#define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
#define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
+#define EEH_DEV_FRESET (1 << 11) /* Fundamental reset */
struct eeh_dev {
int mode; /* EEH mode */