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authorGavin Shan <gwshan@linux.vnet.ibm.com>2014-10-01 17:07:53 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2014-10-15 11:27:20 +1100
commitb6541db1395298b326ae1bf59fae6fbb2c6e8f77 (patch)
tree5f59a01441a5e8c4abaf58f08dbe208a90f5fbe7 /arch/powerpc/kernel/eeh.c
parent3409eb4e69e1150202bc4ec61801115da32aa380 (diff)
powerpc/eeh: Block PCI config access upon frozen PE
The problem was found when I tried to inject PCI config error by PHB3 PAPR error injection registers into Broadcom Austin 4-ports NIC adapter. The frozen PE was reported successfully and EEH core started to recover it. However, I run into fenced PHB when dumping PCI config space as EEH logs. I was told that PCI config requests should not be progagated to the adapter until PE reset is done successfully. Otherise, we would run out of PHB internal credits and trigger PCT (PCIE Completion Timeout), which leads to the fenced PHB. The patch introduces another PE flag EEH_PE_CFG_RESTRICTED, which is set during PE initialization time if the PE includes the specific PCI devices that need block PCI config access until PE reset is done. When the PE becomes frozen for the first time, EEH_PE_CFG_BLOCKED is set if the PE has flag EEH_PE_CFG_RESTRICTED. Then the PCI config access to the PE will be dropped by platform PCI accessors until PE reset is done successfully. The mechanism is shared by PowerNV platform owned PE or userland owned ones. It's not used on pSeries platform yet. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/kernel/eeh.c')
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