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| author | Michael Ellerman <mpe@ellerman.id.au> | 2017-11-10 20:55:03 +1100 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-11-10 20:55:03 +1100 |
| commit | a54c61f46e25345e99eec06a402f746fe33febc6 (patch) | |
| tree | 23f59fe8702aaf90802cef6f25e76c15211747e1 /arch/powerpc/kernel/mce_power.c | |
| parent | 77fad8bfb1d2f8225b05e4ea34457875fcfae37e (diff) | |
| parent | 7ecb37f62fe58e3e4d9b03443b92d213b2c108ce (diff) | |
Merge branch 'fixes' into next
We have some dependencies & conflicts between patches in fixes and
things to go in next, both in the radix TLB flush code and the IMC PMU
driver. So merge fixes into next.
Diffstat (limited to 'arch/powerpc/kernel/mce_power.c')
| -rw-r--r-- | arch/powerpc/kernel/mce_power.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c index 1600ab194ff9..644f7040b91c 100644 --- a/arch/powerpc/kernel/mce_power.c +++ b/arch/powerpc/kernel/mce_power.c @@ -717,5 +717,18 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs) long __machine_check_early_realmode_p9(struct pt_regs *regs) { + /* + * On POWER9 DD2.1 and below, it's possible to get a machine check + * caused by a paste instruction where only DSISR bit 25 is set. This + * will result in the MCE handler seeing an unknown event and the kernel + * crashing. An MCE that occurs like this is spurious, so we don't need + * to do anything in terms of servicing it. If there is something that + * needs to be serviced, the CPU will raise the MCE again with the + * correct DSISR so that it can be serviced properly. So detect this + * case and mark it as handled. + */ + if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000) + return 1; + return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table); } |