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author | Dan Williams <dan.j.williams@intel.com> | 2017-11-15 16:56:11 -0800 |
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committer | Dan Williams <dan.j.williams@intel.com> | 2017-11-15 16:56:11 -0800 |
commit | 4247f24c23589bcc3bc3490515ef8c9497e9ae55 (patch) | |
tree | 89726a0e171c443a3e8def2992b56dbd8a21df21 /arch/powerpc/kernel/mce_power.c | |
parent | 79ab67ede21f536851a99ea68ee6fc1f5435e055 (diff) | |
parent | 9f586fff6574f6ecbf323f92d44ffaf0d96225fe (diff) |
Merge branch 'for-4.15/dax' into libnvdimm-for-next
Diffstat (limited to 'arch/powerpc/kernel/mce_power.c')
-rw-r--r-- | arch/powerpc/kernel/mce_power.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c index b76ca198e09c..72f153c6f3fa 100644 --- a/arch/powerpc/kernel/mce_power.c +++ b/arch/powerpc/kernel/mce_power.c @@ -624,5 +624,18 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs) long __machine_check_early_realmode_p9(struct pt_regs *regs) { + /* + * On POWER9 DD2.1 and below, it's possible to get a machine check + * caused by a paste instruction where only DSISR bit 25 is set. This + * will result in the MCE handler seeing an unknown event and the kernel + * crashing. An MCE that occurs like this is spurious, so we don't need + * to do anything in terms of servicing it. If there is something that + * needs to be serviced, the CPU will raise the MCE again with the + * correct DSISR so that it can be serviced properly. So detect this + * case and mark it as handled. + */ + if (SRR1_MC_LOADSTORE(regs->msr) && regs->dsisr == 0x02000000) + return 1; + return mce_handle_error(regs, mce_p9_derror_table, mce_p9_ierror_table); } |