diff options
| author | Alexander Graf <agraf@suse.de> | 2014-04-29 17:54:40 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-05-30 14:26:23 +0200 |
| commit | 9916d57e64a49d85bcffe272478f869b8fe1583a (patch) | |
| tree | 2afe3777d8c4564ed6b99d74845126f4ae5a031c /arch/powerpc/kvm/book3s_emulate.c | |
| parent | 2e23f544135e7b5fc2f0bcb6fa935c4b4f5058b2 (diff) | |
KVM: PPC: Book3S PR: Expose TM registers
POWER8 introduces transactional memory which brings along a number of new
registers and MSR bits.
Implementing all of those is a pretty big headache, so for now let's at least
emulate enough to make Linux's context switching code happy.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/book3s_emulate.c')
| -rw-r--r-- | arch/powerpc/kvm/book3s_emulate.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index e1165bae693a..9bdff159ad2a 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -451,6 +451,17 @@ int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val) case SPRN_EBBRR: vcpu->arch.ebbrr = spr_val; break; +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + case SPRN_TFHAR: + vcpu->arch.tfhar = spr_val; + break; + case SPRN_TEXASR: + vcpu->arch.texasr = spr_val; + break; + case SPRN_TFIAR: + vcpu->arch.tfiar = spr_val; + break; +#endif #endif case SPRN_ICTC: case SPRN_THRM1: @@ -572,6 +583,17 @@ int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val case SPRN_EBBRR: *spr_val = vcpu->arch.ebbrr; break; +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM + case SPRN_TFHAR: + *spr_val = vcpu->arch.tfhar; + break; + case SPRN_TEXASR: + *spr_val = vcpu->arch.texasr; + break; + case SPRN_TFIAR: + *spr_val = vcpu->arch.tfiar; + break; +#endif #endif case SPRN_THRM1: case SPRN_THRM2: |