diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-06-25 15:08:46 -0500 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-06-27 14:15:54 +1000 |
| commit | 74e27c6af56fe6898c3c8c451595746a992f0f0f (patch) | |
| tree | 592d78385cd5419678bf934c281032b20fb88172 /arch/powerpc/mm/mmu_context_book3s64.c | |
| parent | 8e3f1b1d8255105f31556aacf8aeb6071b00d469 (diff) | |
powerpc: Only do ERAT invalidate on radix context switch on P9 DD1
From: Michael Neuling <mikey@neuling.org>
On P9 (Nimbus) DD2 and later, in radix mode, the move to the PID
register will implicitly invalidate the user space ERAT entries
and leave the kernel ones alone. Thus the only thing needed is
an isync() to synchronize this with subsequent uaccess's
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm/mmu_context_book3s64.c')
| -rw-r--r-- | arch/powerpc/mm/mmu_context_book3s64.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu_context_book3s64.c index c6dca2ae78ef..3ef0a89503bf 100644 --- a/arch/powerpc/mm/mmu_context_book3s64.c +++ b/arch/powerpc/mm/mmu_context_book3s64.c @@ -235,10 +235,15 @@ void destroy_context(struct mm_struct *mm) #ifdef CONFIG_PPC_RADIX_MMU void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next) { - asm volatile("isync": : :"memory"); - mtspr(SPRN_PID, next->context.id); - asm volatile("isync \n" - PPC_SLBIA(0x7) - : : :"memory"); + + if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { + isync(); + mtspr(SPRN_PID, next->context.id); + isync(); + asm volatile(PPC_INVALIDATE_ERAT : : :"memory"); + } else { + mtspr(SPRN_PID, next->context.id); + isync(); + } } #endif |