diff options
| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2020-11-24 15:24:57 +0000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-12-09 23:48:12 +1100 |
| commit | a314ea5abf6dbaf35f14c9bd1d93105260fb9336 (patch) | |
| tree | 923c8dce3f3deb28a56f4f7627ef34e5de51b4db /arch/powerpc/perf/8xx-pmu.c | |
| parent | 576e02bbf1062b9118d5bbb96a40ed3b6b359f22 (diff) | |
powerpc/8xx: Use SPRN_SPRG_SCRATCH2 in ITLB miss exception
In order to re-enable MMU earlier, ensure ITLB miss exception
cannot clobber SPRN_SPRG_SCRATCH0 and SPRN_SPRG_SCRATCH1.
Do so by using SPRN_SPRG_SCRATCH2 and SPRN_M_TW instead, like
the DTLB miss exception.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/abc78e8e9577d473691ebb9996c6413b37bfd9ca.1606231483.git.christophe.leroy@csgroup.eu
Diffstat (limited to 'arch/powerpc/perf/8xx-pmu.c')
| -rw-r--r-- | arch/powerpc/perf/8xx-pmu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/perf/8xx-pmu.c b/arch/powerpc/perf/8xx-pmu.c index e53c3c161257..02db58c7427a 100644 --- a/arch/powerpc/perf/8xx-pmu.c +++ b/arch/powerpc/perf/8xx-pmu.c @@ -165,9 +165,9 @@ static void mpc8xx_pmu_del(struct perf_event *event, int flags) break; case PERF_8xx_ID_ITLB_LOAD_MISS: if (atomic_dec_return(&itlb_miss_ref) == 0) { - /* mfspr r10, SPRN_SPRG_SCRATCH0 */ + /* mfspr r10, SPRN_SPRG_SCRATCH2 */ struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) | - __PPC_SPR(SPRN_SPRG_SCRATCH0)); + __PPC_SPR(SPRN_SPRG_SCRATCH2)); patch_instruction_site(&patch__itlbmiss_exit_1, insn); } |