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authorOliver O'Halloran <oohall@gmail.com>2020-07-22 16:57:14 +1000
committerMichael Ellerman <mpe@ellerman.id.au>2020-07-26 23:34:23 +1000
commit4c51f3e1e8702cbd0e53159fc3d1f54c20c70574 (patch)
treea145cb717ab069ae3f78fb0c3decebd3b5c1abc7 /arch/powerpc/platforms/powernv/pci.h
parenta0be516f8160fdb4836237cba037229e88a1de7d (diff)
powerpc/powernv/sriov: Make single PE mode a per-BAR setting
Using single PE BARs to map an SR-IOV BAR is really a choice about what strategy to use when mapping a BAR. It doesn't make much sense for this to be a global setting since a device might have one large BAR which needs to be mapped with single PE windows and another smaller BAR that can be mapped with a regular segmented window. Make the segmented vs single decision a per-BAR setting and clean up the logic that decides which mode to use. Signed-off-by: Oliver O'Halloran <oohall@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200722065715.1432738-15-oohall@gmail.com
Diffstat (limited to 'arch/powerpc/platforms/powernv/pci.h')
-rw-r--r--arch/powerpc/platforms/powernv/pci.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 41a6f4e938e4..902e928c7c22 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -243,8 +243,15 @@ struct pnv_iov_data {
/* pointer to the array of VF PEs. num_vfs long*/
struct pnv_ioda_pe *vf_pe_arr;
- /* Did we map the VF BARs with single-PE IODA BARs? */
- bool m64_single_mode;
+ /* Did we map the VF BAR with single-PE IODA BARs? */
+ bool m64_single_mode[PCI_SRIOV_NUM_BARS];
+
+ /*
+ * True if we're using any segmented windows. In that case we need
+ * shift the start of the IOV resource the segment corresponding to
+ * the allocated PE.
+ */
+ bool need_shift;
/*
* Bit mask used to track which m64 windows are used to map the