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authorChristophe Leroy <christophe.leroy@c-s.fr>2016-08-23 15:58:56 +0200
committerScott Wood <oss@buserror.net>2016-09-25 02:38:53 -0500
commit834e5a692120cc25c3935e8652a1989c2bc1c9e9 (patch)
tree7b9707625fe89d567ceef4f6a8816807a3de5f3d /arch/powerpc/sysdev/fsl_pci.c
parentfff69fd03d1290297fcd039b07819fafa69ffc0a (diff)
powerpc/8xx: use SPRN_EIE and SPRN_EID to enable/disable interrupts
The 8xx has two special registers called EID (External Interrupt Disable) and EIE (External Interrupt Enable) for clearing/setting EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or mfmsr/rlwinm/mtmsr and it avoids using a general register. We just have to write something in the special register to change MSR EE bit. So we write r0 into the register, regardless of r0 value. Writing to one of those two special registers also set the MSR RI bit, but this bit is only unset during beginning of exception prolog and end of exception epilog. When executing C-functions MSR RI is always set. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.c')
0 files changed, 0 insertions, 0 deletions