diff options
| author | Damien Le Moal <damien.lemoal@wdc.com> | 2021-01-12 09:58:40 +0900 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-02-18 23:18:01 -0800 |
| commit | d4c34d09ab03e1e631fe195ddf35365a1273be9c (patch) | |
| tree | 0c942a73fbaf73c97b3bf3a16557554116ef78c3 /arch/riscv/Kconfig.socs | |
| parent | 5da9cbd2b200369fd190c81bc1253e9a17ab3e8d (diff) | |
pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver
Add the pinctrl-k210.c pinctrl driver for the Canaan Kendryte K210
field programmable IO array (FPIOA) to allow configuring the SoC pin
functions. The K210 has 48 programmable pins which can take any of 256
possible functions.
This patch is inspired from the k210 pinctrl driver for the u-boot
project and contains many direct contributions from Sean Anderson.
The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210
SOC FPIOA DRIVER" with myself listed as maintainer for this driver.
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/Kconfig.socs')
| -rw-r--r-- | arch/riscv/Kconfig.socs | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 57e53219c500..6402746c68f3 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -30,6 +30,7 @@ config SOC_CANAAN select SERIAL_SIFIVE_CONSOLE if TTY select SIFIVE_PLIC select ARCH_HAS_RESET_CONTROLLER + select PINCTRL help This enables support for Canaan Kendryte K210 SoC platform hardware. |