diff options
author | Ingo Molnar <mingo@kernel.org> | 2020-01-06 07:51:15 +0100 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2020-01-06 07:51:15 +0100 |
commit | 31c7ac388aa905a196ee16dff2015111f701f035 (patch) | |
tree | 09a43dde7fbf30ce57eaf5ba7ebda84da961538d /arch/riscv/boot/dts/sifive/fu540-c000.dtsi | |
parent | 28336be568bb473d16ba80db0801276fb4f1bbe5 (diff) | |
parent | c79f46a282390e0f5b306007bf7b11a46d529538 (diff) |
Merge tag 'v5.5-rc5' into locking/kcsan, to resolve conflict
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/riscv/boot/dts/sifive/fu540-c000.dtsi')
-rw-r--r-- | arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 70a1891e7cd0..a2e3d54e830c 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -54,6 +54,7 @@ reg = <1>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -77,6 +78,7 @@ reg = <2>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -100,6 +102,7 @@ reg = <3>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -123,6 +126,7 @@ reg = <4>; riscv,isa = "rv64imafdc"; tlb-split; + next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -253,6 +257,17 @@ #pwm-cells = <3>; status = "disabled"; }; + l2cache: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; }; }; |