diff options
| author | William Qiu <william.qiu@starfivetech.com> | 2023-12-22 17:45:47 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2024-01-22 21:00:03 +0000 |
| commit | 5e598b99fedf57858a98c5edf9da55e378910781 (patch) | |
| tree | b865de09007a28efc64c81618d3c41c7aa5880c3 /arch/riscv/boot/dts/starfive/jh7100-common.dtsi | |
| parent | 2529085831b01fcd02ff58ab4e2596d3b31bcf80 (diff) | |
riscv: dts: starfive: jh7100: Add PWM node and pins configuration
Add OpenCores PWM controller node and add PWM pins configuration
on VisionFive 1 board.
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot/dts/starfive/jh7100-common.dtsi')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100-common.dtsi | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index 42fb61c36068..6aac0404b465 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -115,6 +115,24 @@ }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = <GPIOMUX(7, + GPO_PWM_PAD_OUT_BIT0, + GPO_PWM_PAD_OE_N_BIT0, + GPI_NONE)>, + <GPIOMUX(5, + GPO_PWM_PAD_OUT_BIT1, + GPO_PWM_PAD_OE_N_BIT1, + GPI_NONE)>; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + sdio0_pins: sdio0-0 { clk-pins { pinmux = <GPIOMUX(54, GPO_SDIO0_PAD_CCLK_OUT, @@ -257,6 +275,12 @@ clock-frequency = <27000000>; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &sdio0 { broken-cd; bus-width = <4>; |