diff options
| author | Jia Jie Ho <jiajie.ho@starfivetech.com> | 2023-08-08 22:15:58 +0800 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2023-08-09 19:43:51 +0100 |
| commit | 87ddf5b1096467d24584ea61de0580776722d961 (patch) | |
| tree | 326f27454bfed3f3e936e72416c3241d75cf6208 /arch/riscv/boot/dts | |
| parent | e2c07765e179d0849326d4e1bd62ef8ba3d3cfd1 (diff) | |
riscv: dts: starfive - Add hwrng node for JH7110 SoC
Add hardware rng controller node for StarFive JH7110 SoC.
Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot/dts')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 96fb88e702a6..c2b401f4d803 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -848,6 +848,16 @@ #dma-cells = <2>; }; + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + interrupts = <30>; + }; + mmc0: mmc@16010000 { compatible = "starfive,jh7110-mmc"; reg = <0x0 0x16010000 0x0 0x10000>; |