diff options
| author | Christoph Hellwig <hch@lst.de> | 2019-10-28 13:10:40 +0100 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-11-17 15:17:39 -0800 |
| commit | 9e80635619b51ddc56bdeca4da4056eb7a2a77e0 (patch) | |
| tree | fda5d1465f1130cd9cc21920112e28b4ed7028c5 /arch/riscv/include/asm/csr.h | |
| parent | accb9dbc4affdb7ebf30db7e9ba71eee47280081 (diff) | |
riscv: clear the instruction cache and all registers when booting
When we get booted we want a clear slate without any leaks from previous
supervisors or the firmware. Flush the instruction cache and then clear
all registers to known good values. This is really important for the
upcoming nommu support that runs on M-mode, but can't really harm when
running in S-mode either. Vaguely based on the concepts from opensbi.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Diffstat (limited to 'arch/riscv/include/asm/csr.h')
| -rw-r--r-- | arch/riscv/include/asm/csr.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 318192c66fd8..0a62d2d68455 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -92,6 +92,7 @@ #define CSR_SATP 0x180 #define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 #define CSR_MSCRATCH 0x340 |