diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2023-03-06 12:10:15 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-04-21 17:45:42 +0530 |
| commit | 8fe6f7e14c7eeb01c3a1994eba2356400981cb1e (patch) | |
| tree | 574862e1bc8bea264ecc2715322ad501d1c0b852 /arch/riscv/include/asm/hwcap.h | |
| parent | d6f5f6e904be628941eeab7d6ae7d1fb9190c486 (diff) | |
RISC-V: Detect AIA CSRs from ISA string
We have two extension names for AIA ISA support: Smaia (M-mode AIA CSRs)
and Ssaia (S-mode AIA CSRs).
We extend the ISA string parsing to detect Smaia and Ssaia extensions.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/asm/hwcap.h')
| -rw-r--r-- | arch/riscv/include/asm/hwcap.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6263a0de1c6a..74f5dab2148f 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -42,6 +42,8 @@ #define RISCV_ISA_EXT_ZBB 30 #define RISCV_ISA_EXT_ZICBOM 31 #define RISCV_ISA_EXT_ZIHINTPAUSE 32 +#define RISCV_ISA_EXT_SMAIA 33 +#define RISCV_ISA_EXT_SSAIA 34 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 |