diff options
| author | Samuel Holland <samuel.holland@sifive.com> | 2024-02-27 22:55:33 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-02-29 10:20:16 -0800 |
| commit | 3fb3f7164edc467450e650dca51dbe4823315a56 (patch) | |
| tree | 0389030fbd3a9d8adf5b9448c55115caa05b6603 /arch/riscv/include/asm/hwcap.h | |
| parent | 6613476e225e090cc9aad49be7fa504e290dd33d (diff) | |
riscv: Fix enabling cbo.zero when running in M-mode
When the kernel is running in M-mode, the CBZE bit must be set in the
menvcfg CSR, not in senvcfg.
Cc: <stable@vger.kernel.org>
Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240228065559.3434837-2-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/asm/hwcap.h')
0 files changed, 0 insertions, 0 deletions