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authorPalmer Dabbelt <palmer@sifive.com>2017-12-01 13:12:10 -0800
committerPalmer Dabbelt <palmer@sifive.com>2017-12-01 13:12:10 -0800
commit07f8ba7439f9c942d5bd7b63074e7a1528601713 (patch)
treea9ea3bf949955e5808617e4b21372c0ed85bc009 /arch/riscv/include/asm/tlbflush.h
parentf8182f613c9887744eb469b1a3352636481cb395 (diff)
parent0e710ac6521f13c68a5c634471f40ae448c31e0a (diff)
RISC-V: User-Visible Changes
This merge contains the user-visible, ABI-breaking changes that we want to make sure we have in Linux before our first release. Highlights include: * VDSO entries for clock_get/gettimeofday/getcpu have been added. These are simple syscalls now, but we want to let glibc use them from the start so we can make them faster later. * A VDSO entry for instruction cache flushing has been added so userspace can flush the instruction cache. * The VDSO symbol versions for __vdso_cmpxchg{32,64} have been removed, as those VDSO entries don't actually exist. Conflicts: arch/riscv/include/asm/tlbflush.h
Diffstat (limited to 'arch/riscv/include/asm/tlbflush.h')
-rw-r--r--arch/riscv/include/asm/tlbflush.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index c79fab3d377d..715b0f10af58 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -17,6 +17,8 @@
#ifdef CONFIG_MMU
+#include <linux/mm_types.h>
+
/*
* Flush entire local TLB. 'sfence.vma' implicitly fences with the instruction
* cache as well, so a 'fence.i' is not necessary.