diff options
| author | Mayuresh Chitale <mchitale@ventanamicro.com> | 2023-09-13 22:08:59 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-10-12 18:33:27 +0530 |
| commit | 9dbaf381008dfa2fad6225633004f7adb1bac252 (patch) | |
| tree | b0ecd83778851aaf7eeafdc3a7b3f8a29629f851 /arch/riscv/include/asm | |
| parent | 94f6f0550c625fab1f373bb86a6669b45e9748b3 (diff) | |
RISC-V: Detect Smstateen extension
Extend the ISA string parsing to detect the Smstateen extension. If the
extension is enabled then access to certain 'state' such as AIA CSRs in
VS mode is controlled by *stateen0 registers.
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include/asm')
| -rw-r--r-- | arch/riscv/include/asm/hwcap.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b7b58258f6c7..0f520f7d058a 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -58,6 +58,7 @@ #define RISCV_ISA_EXT_ZICSR 40 #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 +#define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_MAX 64 |