Merge tag 'riscv-for-linus-6.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

 - Fixes for a pair of kexec_file_load() failures

 - A fix to ensure the direct mapping is PMD-aligned

 - A fix for CPU feature detection on SMP=n

 - The MMIO ordering fences have been strengthened to ensure ordering
   WRT delay()

 - Fixes for a pair of -Wmissing-variable-declarations warnings

 - A fix to avoid PUD mappings in vmap on sv39

 - flush_cache_vmap() now flushes the TLB to avoid issues on systems
   that cache invalid mappings

* tag 'riscv-for-linus-6.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  riscv: Implement flush_cache_vmap()
  riscv: Do not allow vmap pud mappings for 3-level page table
  riscv: mm: fix 2 instances of -Wmissing-variable-declarations
  riscv,mmio: Fix readX()-to-delay() ordering
  riscv: Fix CPU feature detection with SMP disabled
  riscv: Start of DRAM should at least be aligned on PMD size for the direct mapping
  riscv/kexec: load initrd high in available memory
  riscv/kexec: handle R_RISCV_CALL_PLT relocation type

1 files changed, 5 insertions, 0 deletions

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index a2fc952318e9..35b854cf078e 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -17,6 +17,11 @@
 #include <asm/smp.h>
 #include <asm/pgtable.h>
 
+bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
+{
+	return phys_id == cpuid_to_hartid_map(cpu);
+}
+
 /*
  * Returns the hart ID of the given device tree node, or -ENODEV if the node
  * isn't an enabled and valid RISC-V hart node.