diff options
| author | Anup Patel <Anup.Patel@wdc.com> | 2019-04-25 08:38:41 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-05-16 20:42:11 -0700 |
| commit | a3182c91ef4e7dda90ff080a4132efd3ecb8786a (patch) | |
| tree | 5309b2480f3c6bb9e6df4d7921c7a71ce18dcc4d /arch/riscv/kernel/head.S | |
| parent | 6dcaf00487ca10d87e53fc8decb2e30f113c955d (diff) | |
RISC-V: Access CSRs using CSR numbers
We should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not recognize
newly addes CSRs by name.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/kernel/head.S')
| -rw-r--r-- | arch/riscv/kernel/head.S | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 478821d31bb3..987d4648aad9 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -22,9 +22,9 @@ __INIT ENTRY(_start) - /* Mask and clear all interrupts */ - csrw sie, zero - csrw sip, zero + /* Mask all interrupts */ + csrw CSR_SIE, zero + csrw CSR_SIP, zero /* Load the global pointer */ .option push @@ -86,7 +86,7 @@ relocate: /* Point stvec to virtual address of intruction after satp write */ la a0, 1f add a0, a0, a1 - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Compute satp for kernel page tables, but don't load it yet */ la a2, swapper_pg_dir @@ -102,12 +102,12 @@ relocate: srl a0, a0, PAGE_SHIFT or a0, a0, a1 sfence.vma - csrw sptbr, a0 + csrw CSR_SATP, a0 .align 2 1: /* Set trap vector to spin forever to help debug */ la a0, .Lsecondary_park - csrw stvec, a0 + csrw CSR_STVEC, a0 /* Reload the global pointer */ .option push @@ -116,7 +116,7 @@ relocate: .option pop /* Switch to kernel page tables */ - csrw sptbr, a2 + csrw CSR_SATP, a2 ret @@ -127,7 +127,7 @@ relocate: /* Set trap vector to spin forever to help debug */ la a3, .Lsecondary_park - csrw stvec, a3 + csrw CSR_STVEC, a3 slli a3, a0, LGREG la a1, __cpu_up_stack_pointer |