diff options
| author | Atish Patra <atish.patra@wdc.com> | 2020-03-17 18:11:43 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-03-31 11:27:50 -0700 |
| commit | cfafe260137418d0265d0df3bb18dc494af2b43e (patch) | |
| tree | 50bde642415f253c2f4bf848fcb5441af43f2c79 /arch/riscv/kernel/traps.c | |
| parent | db5a79460315bd12dedee5f964cd72f3a534ecb2 (diff) | |
RISC-V: Add supported for ordered booting method using HSM
Currently, all harts have to jump Linux in RISC-V. This complicates the
multi-stage boot process as every transient stage also has to ensure all
harts enter to that stage and jump to Linux afterwards. It also obstructs
a clean Kexec implementation.
SBI HSM extension provides alternate solutions where only a single hart
need to boot and enter Linux. The booting hart can bring up secondary
harts one by one afterwards.
Add SBI HSM based cpu_ops that implements an ordered booting method in
RISC-V. This change is also backward compatible with older firmware not
implementing HSM extension. If a latest kernel is used with older
firmware, it will continue to use the default spinning booting method.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'arch/riscv/kernel/traps.c')
| -rw-r--r-- | arch/riscv/kernel/traps.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index a4d136355f78..23a57b92cd1d 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -148,7 +148,7 @@ int is_valid_bugaddr(unsigned long pc) } #endif /* CONFIG_GENERIC_BUG */ -void __init trap_init(void) +void trap_init(void) { /* * Set sup0 scratch register to 0, indicating to exception vector |