diff options
| author | Anup Patel <apatel@ventanamicro.com> | 2022-05-09 10:43:52 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-05-20 09:09:09 +0530 |
| commit | 2415e46e3a9a22c80eddc41dc9cb0b06fe0cd5e9 (patch) | |
| tree | 7a23d030a7a214c983efac02485b5bd39461655f /arch/riscv/kvm/mmu.c | |
| parent | c7fa3c48de86053b0f1949fa5532082544e30fce (diff) | |
RISC-V: KVM: Introduce range based local HFENCE functions
Various __kvm_riscv_hfence_xyz() functions implemented in the
kvm/tlb.S are equivalent to corresponding HFENCE.GVMA instructions
and we don't have range based local HFENCE functions.
This patch provides complete set of local HFENCE functions which
supports range based TLB invalidation and supports HFENCE.VVMA
based functions. This is also a preparatory patch for upcoming
Svinval support in KVM RISC-V.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kvm/mmu.c')
| -rw-r--r-- | arch/riscv/kvm/mmu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c index 8823eb32dcde..1e07603c905b 100644 --- a/arch/riscv/kvm/mmu.c +++ b/arch/riscv/kvm/mmu.c @@ -745,7 +745,7 @@ void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu) csr_write(CSR_HGATP, hgatp); if (!kvm_riscv_gstage_vmid_bits()) - __kvm_riscv_hfence_gvma_all(); + kvm_riscv_local_hfence_gvma_all(); } void kvm_riscv_gstage_mode_detect(void) @@ -768,7 +768,7 @@ void kvm_riscv_gstage_mode_detect(void) skip_sv48x4_test: csr_write(CSR_HGATP, 0); - __kvm_riscv_hfence_gvma_all(); + kvm_riscv_local_hfence_gvma_all(); #endif } |