diff options
| author | Alexandre Ghiti <alexandre.ghiti@canonical.com> | 2022-07-11 09:29:51 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-07-11 09:33:35 +0530 |
| commit | 88573389aaa34640b9ecde15622c68e8737d8f8c (patch) | |
| tree | 098415c3502e72e47adfe195cb3ff5861934a07e /arch/riscv/kvm/mmu.c | |
| parent | 32346491ddf24599decca06190ebca03ff9de7f8 (diff) | |
riscv: Fix missing PAGE_PFN_MASK
There are a bunch of functions that use the PFN from a page table entry
that end up with the svpbmt upper-bits because they are missing the newly
introduced PAGE_PFN_MASK which leads to wrong addresses conversions and
then crash: fix this by adding this mask.
Fixes: 100631b48ded ("riscv: Fix accessing pfn bits in PTEs for non-32bit variants")
Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kvm/mmu.c')
| -rw-r--r-- | arch/riscv/kvm/mmu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c index 1c00695ebee7..9826073fbc67 100644 --- a/arch/riscv/kvm/mmu.c +++ b/arch/riscv/kvm/mmu.c @@ -54,7 +54,7 @@ static inline unsigned long gstage_pte_index(gpa_t addr, u32 level) static inline unsigned long gstage_pte_page_vaddr(pte_t pte) { - return (unsigned long)pfn_to_virt(pte_val(pte) >> _PAGE_PFN_SHIFT); + return (unsigned long)pfn_to_virt(__page_val_to_pfn(pte_val(pte))); } static int gstage_page_size_to_level(unsigned long page_size, u32 *out_level) |