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authorAtish Patra <atish.patra@wdc.com>2018-10-02 12:14:58 -0700
committerPalmer Dabbelt <palmer@sifive.com>2018-10-22 17:03:36 -0700
commit6db170ff4c088caaf7806c00b29a55f6df07d7b6 (patch)
treed91d87868100acbbf8436728ebcdccc152689766 /arch/riscv
parentb18d6f05252d6b3f725c08d8831a46b003df5b6b (diff)
RISC-V: Disable preemption before enabling interrupts
Currently, irq is enabled before preemption disabling happens. If the scheduler fired right here and cpu is scheduled then it may blow up. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> [Atish: Commit text and code comment formatting update] Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/kernel/smpboot.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 712e9ca85904..670749ecd0c2 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -111,7 +111,11 @@ asmlinkage void __init smp_callin(void)
* a local TLB flush right now just in case.
*/
local_flush_tlb_all();
- local_irq_enable();
+ /*
+ * Disable preemption before enabling interrupts, so we don't try to
+ * schedule a CPU that hasn't actually started yet.
+ */
preempt_disable();
+ local_irq_enable();
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}