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authorAtish Patra <atish.patra@wdc.com>2018-10-02 12:15:03 -0700
committerPalmer Dabbelt <palmer@sifive.com>2018-10-22 17:03:37 -0700
commita37d56fc401108f39dec9ba83ed923a453937a26 (patch)
treeb050e592dc352a44bddc333ead5602abbab2e7a4 /arch/riscv
parent46373cb442c56d2f8a4c8b3f777c89d20546c9d5 (diff)
RISC-V: Use WRITE_ONCE instead of direct access
The secondary harts spin on couple of per cpu variables until both of these are non-zero so it's not necessary to have any ordering here. However, WRITE_ONCE should be used to avoid tearing. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/kernel/smpboot.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 17e748312afd..1e478615017c 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -81,8 +81,9 @@ int __cpu_up(unsigned int cpu, struct task_struct *tidle)
* the spinning harts that they can continue the boot process.
*/
smp_mb();
- __cpu_up_stack_pointer[cpu] = task_stack_page(tidle) + THREAD_SIZE;
- __cpu_up_task_pointer[cpu] = tidle;
+ WRITE_ONCE(__cpu_up_stack_pointer[cpu],
+ task_stack_page(tidle) + THREAD_SIZE);
+ WRITE_ONCE(__cpu_up_task_pointer[cpu], tidle);
while (!cpu_online(cpu))
cpu_relax();