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authorPalmer Dabbelt <palmer@sifive.com>2019-03-26 17:40:24 -0700
committerPalmer Dabbelt <palmer@sifive.com>2019-05-16 20:42:13 -0700
commit4c3aeb82a0f4612bf0d94fbf74c3738db2c32fe5 (patch)
tree3a20f1f44c668fe3118550c2bb0a319ba8b9da96 /arch/riscv
parent9a6e7af02f7fcc8c68e9d6ce167ee6ab0052cb60 (diff)
RISC-V: Avoid using invalid intermediate translations
This is almost entirely a comment. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/kernel/head.S12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S
index 987d4648aad9..370c66ce187a 100644
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -96,7 +96,9 @@ relocate:
/*
* Load trampoline page directory, which will cause us to trap to
- * stvec if VA != PA, or simply fall through if VA == PA
+ * stvec if VA != PA, or simply fall through if VA == PA. We need a
+ * full fence here because setup_vm() just wrote these PTEs and we need
+ * to ensure the new translations are in use.
*/
la a0, trampoline_pg_dir
srl a0, a0, PAGE_SHIFT
@@ -115,8 +117,14 @@ relocate:
la gp, __global_pointer$
.option pop
- /* Switch to kernel page tables */
+ /*
+ * Switch to kernel page tables. A full fence is necessary in order to
+ * avoid using the trampoline translations, which are only correct for
+ * the first superpage. Fetching the fence is guarnteed to work
+ * because that first superpage is translated the same way.
+ */
csrw CSR_SATP, a2
+ sfence.vma
ret